2023年6月24日发(作者：)

4Gb: x4, x8, x16 DDR3L SDRAMPRECHARGE OperationPRECHARGE OperationInput A10 determines whether one bank or all banks are to be precharged and, in thecase where only one bank is to be precharged, inputs BA[2:0] select the all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After abank is precharged, it is in the idle state and must be activated prior to any READ orWRITE commands being REFRESH OperationThe SELF REFRESH operation is initiated like a REFRESH command except CKE is DLL is automatically disabled upon entering SELF REFRESH and is automaticallyenabled and reset upon exiting SELF power supply inputs (including VREFCA and VREFDQ) must be maintained at valid lev-els upon entry/exit and during self refresh mode operation. VREFDQ may float or notdrive VDDQ/2 while in self refresh mode under certain conditions:••••VSS < VREFDQ < VDD is is valid and stable prior to CKE going back first WRITE operation may not occur earlier than 512 clocks after VREFDQ is other self refresh mode exit timing requirements are DRAM must be idle with all banks in the precharge state (tRP is satisfied and nobursts are in progress) before a self refresh entry command can be issued. ODT mustalso be turned off before self refresh entry by registering the ODT ball LOW prior to theself refresh entry command (see On-Die Termination (ODT) ( for timing requirements).If RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”After the self refresh entry command is registered, CKE must be held LOW to keep theDRAM in self refresh the DRAM has entered self refresh mode, all external control signals, except CKEand RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-mand internally within the

tCKE period when it enters self refresh requirements for entering and exiting self refresh mode depend on the state of theclock during self refresh mode. First and foremost, the clock must be stable (meetingtCK specifications) when self refresh mode is entered. If the clock remains stable andthe frequency is not altered while in self refresh mode, then the DRAM is allowed to exitself refresh mode after

tCKESR is satisfied (CKE is allowed to transition HIGH

tCKESRlater than when CKE was registered LOW). Since the clock remains stable in self refreshmode (no frequency change),

tCKSRE and

tCKSRX are not required. However, if theclock is altered during self refresh mode (if it is turned-off or its frequency changes),then

tCKSRE and

tCKSRX must be satisfied. When entering self refresh mode,

tCKSREmust be satisfied prior to altering the clock's frequency. Prior to exiting self refreshmode,

tCKSRX must be satisfied prior to registering CKE CKE is HIGH during self refresh exit, NOP or DES must be issued for

tXS time.

tXSis required for the completion of any internal refresh already in progress and must besatisfied before a valid command not requiring a locked DLL can be issued to the de-vice.

tXS is also the earliest time self refresh re-entry may occur. Before a command re-quiring a locked DLL can be applied, a ZQCL command must be issued,

tZQOPER tim-ing must be met, and

tXSDLL must be satisfied. ODT must be off during

tXSDLL.4Gb: x4, x8, x16 DDR3L SDRAMPower-Down Modeexit mode precharge power-down. A summary of the two power-down modes is listed in

Table 82 (page 188).While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stableclock signal must be maintained. ODT must be in a valid state but all other input signalsare “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out ofpower-down mode and go into the reset state. After CKE is registered LOW, CKE mustremain LOW until

tPD (MIN) has been satisfied. The maximum time allowed for power-down duration is

tPD (MAX) (9 ×

tREFI).The power-down states are synchronously exited when CKE is registered HIGH (with arequired NOP or DES command). CKE must be maintained HIGH until

tCKE has beensatisfied. A valid, executable command may be applied after power-down exit latency,tXP, and

tXPDLL have been satisfied. A summary of the power-down modes is listed specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-to-power-down-entry sequence, the number of clock cycles between power-down exitand power-down entry may not be sufficient to keep the DLL properly updated. In addi-tion to meeting

tPD when the REFRESH command is used between power-down exitand power-down entry, two other conditions must be met. First,

tXP must be satisfiedbefore issuing the REFRESH command. Second,

tXPDLL must be satisfied before thenext power-down may be entered. An example is shown in Figure 108 (page 194).Table 82: Power-Down ModesDRAM StateActive (any bank open)Precharged(all banks precharged)MR0[12]“Don’t Care”10DLL StateOnOnOffPower-Down ExitFastFastSlowRelevant ParameterstXP to any other valid commandtXP to any other valid commandtXPDLL to commands that require the DLL to belocked (READ, RDAP, or ODT on);tXP to any other valid command4Gb: x4, x8, x16 DDR3L SDRAMPower-Down ModeFigure 104: REFRESH to Power-Down EntryT0CK#CKtCKtCHtCLT1T2T3Ta0Ta1Ta2Tb0CommandREFRESHNOPtCPDEDtISNOPNOPNOPValidtCKE (MIN)tPDCKEtREFPDENtXP (MIN)tRFC (MIN)1Indicates breakin time scaleDon’t CareNote: CKE goes HIGH during

tRFC, CKE must remain HIGH until

tRFC is 105: ACTIVATE to Power-Down EntryT0CK#CKtCKtCHtCLT1T2T3T4T5T6T7CommandACTIVENOPNOPAddressValidtCPDEDtIStPDCKEtACTPDENDon’t Care