2023年6月24日发(作者：)

元器件交易网tures•Low-voltage and Standard-voltage Operation–2.7 (VCC = 2.7V to 5.5V)–1.8 (V•CC = 1.8V to 5.5V)User Selectable Internal Organization–16K: 2048 x 8 or 1024 x 16•3-wire Serial Interface•Sequential Read Operation•Schmitt Trigger, Filtered Inputs for Noise Suppression•2 MHz Clock Rate (5V) Compatibility•Self-timed Write Cycle (10 ms max)•High Reliability–Endurance: 1 Million Write Cycles–Data Retention: 100 Years•Automotive Grade, Extended Temperature and Lead-Free/Halogen-FreeDevices Available•8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP PackagesDescriptionThe AT93C86A provides 16384 bits of serial electrically erasable programmable readonly memory (EEPROM) organized as 1024 words of 16 bits each when the ORG Pinis connected to Vdevice is optimized for use in many industrial and commercial applications where lowCC and 2048 words of 8 bits each when it is tied to ground. Thepower and low voltage operations are essential. The AT93C86A is available in spacesaving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP ConfigurationsPin NameFunction8-lead PDIPCSChip SelectCS18VCCSKSerial Data ClockSK27DCDISerial Data InputDI36ORGDOSerial Data OutputDO45GNDGNDGroundVCCPower Supply8-lead SOICORGInternal OrganizationDCDon’t ConnectCS18VCCSK27DCDI36ORG8-lead MAPDO45GNDVCC81CSDC72SK8-lead TSSOPORG63DIGNDCS18VCC54DOSK27DCDI36ORGBottom ViewDO45GND3-wire SerialEEPROM16K (2048 x 8 or 1024 x 16)AT93C86APreliminaryRev. 3408C–SEEPR–1/041元器件交易网 AT93C86A is enabled through the Chip Select pin (CS), and accessed via a 3-wireserial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK).Upon receiving a READ instruction at DI, the address is decoded and the data isclocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle isonly enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought“high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSYstatus of the part. The AT93C86A is available in a 2.7V to 5.5V version.

Absolute Maximum Ratings*-55°C to +125°-65°C to +150°CVoltage on any Pinwith Respect .-1.0V to +7.0VMaximum 6.25VDC 5.0 mA*NOTICE:Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliabilityBlock Diagram

VccGNDMEMORY ARRAYORG2048 x 8OR1024 x 16ADDRESSDECODERDATAREGISTERDIMODEDECODELOGICOUTPUTBUFFERCSSKCLOCKGENERATORDONote: the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of theinternal 1 Meg ohm pullup, then the x 16 organization is selected. This feature is not available on the 1.8V devices.2AT93C86A [Preliminary]3408C–SEEPR–1/04元器件交易网93C86A [Preliminary]Pin Capacitance(1)Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).SymbolCOUTCINNote:Test ConditionsOutput Capacitance (DO)Input Capacitance (CS, SK, DI) parameter is characterized and is not 100% 55UnitspFpFConditionsVOUT = 0VVIN = 0VDC CharacteristicsApplicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,

TAE = -40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted).SymbolVCC1VCC2VCC3ICCISB1ISB2ISB3IILIOLVIL1(1)VIH1(1)VIL2(1)VIH2(1)VOL1VOH1VOL2VOH2Note:ParameterSupply VoltageSupply VoltageSupply VoltageSupply CurrentStandby CurrentStandby CurrentStandby CurrentInput LeakageOutput LeakageInput Low VoltageInput High VoltageInput Low VoltageInput High VoltageOutput Low VoltageOutput High VoltageOutput Low VoltageOutput High VoltageVCC = 5.0VVCC = 1.8VVCC = 2.7VVCC = 5.0VREAD at 1.0 MHzWRITE at 1.0 MHzCS = 0VCS = 0VCS = 0VTest ConditionMin1.82.74.50.50.506.017TypMax5.55.55.52.02.00.110.0303.03.00.8VCC + 1VCC x 0.3VCC + 10.42.40.2VCC - 0.2UnitVVVmAmAµAµAµAµAµAVVVVVVVIN = 0V to VCC 0.1VIN = 0V to VCC 0.12.7V ≤ VCC ≤ 5.5V 2.7V1.8V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤IOL = 2.1 mAIOH = -0.4 mAIOL = 0.15 mAIOH = -100 µA-0.62.0-0.6VCC x 0.71.8V ≤ VCC ≤ min and VIH max are reference only and are not tested.33408C–SEEPR–1/04元器件交易网 CharacteristicsApplicable over recommended operating range from TAI = -40°C to + 85°C, TAE = -40°C to +125°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted).SymbolfSKParameterSK Clock

FrequencySK High TimeSK Low TimeMinimum CS

Low TimeCS Setup TimeDI Setup TimeCS Hold TimeDI Hold TimeOutput Delay to ‘1’Output Delay to ‘0’CS to Status ValidCS to DO in High

ImpedanceWrite Cycle Time5.0V, 25°C, Page ModeTest Condition4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤ 5.5V 5.5V2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤ 5.5VRelative to SKRelative to SKRelative to SKRelative to SKAC TestAC TestAC TestAC TestCS = VIL 5.5V2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤1.8V ≤ VCC ≤ 5.5V 5.5V2.7V ≤ VCC ≤1.8V ≤ VCC ≤ 5.5V 5.5V2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤2.7V ≤ VCC ≤ 5.5V 5.5V1.8V ≤ VCC ≤2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤ 5.5V 5.5V2.7V ≤ VCC ≤ 5.5V1.8V ≤ VCC ≤Min525150400104.5V ≤ VCC ≤ 5.5V1M4TypMax210.25UnitsMHztSKHtSKLtCStCSStDIStCSHtDIHtPD1tPD0tSVtDFtWPEndurance(1)nsnsnsnsnsnsnsnsnsnsnsmsmsWrite CyclesNote: parameter is characterized and is not 100% tested.

4AT93C86A [Preliminary]3408C–SEEPR–1/04元器件交易网93C86A [Preliminary]Instruction Set for the AT93C86AAddressInstructionREADEWENERASEWRITEERALWRALSB111111Op Code1x 8A10 - A011XXXXXXXXA10

- A0A10 - A010XXXXXXXX01XXXXXXXXx 16A9 - A011XXXXXXXXA9 -

A0A9

- A010XXXXXXXX01XXXXXXXXD7 - D0D15

- D0D7

- D0D15

- D0x 8Datax 16CommentsReads data stored in memory,

at specified enable must precede all

programming memory location An - memory location An - all memory locations.

Valid only at VCC = 4.5V to all memory locations.

Valid when VCC = 4.5V to 5.5V and

Disable Register es all programming 10000XXXXXXXX00XXXXXXXXFunctional

DescriptionThe AT93C86A is accessed via a simple and versatile 3-wire serial communicationinterface. Device operation is controlled by seven instructions issued by the host pro-cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit(logic “1”) followed by the appropriate Op Code and the desired memory (READ): The Read (READ) instruction contains the Address code for the mem-ory location to be read. After the instruction and address are decoded, data from theselected memory location is available at the serial output pin DO. Output data changesare synchronized with the rising edges of serial clock SK. It should be noted that adummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A sup-ports sequential read operations. The device will automatically increment the internaladdress pointer and clock out the next memory location as long as Chip Select (CS) isheld high. In this case, the dummy bit (logic “0”) will not be clocked out between memorylocations, thus allowing for a continuous stream of data to be /WRITE (EWEN): To assure data integrity, the part automatically goes into theErase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable(EWEN) instruction must be executed first before any programming instructions can becarried out. Please note that once in the Erase/Write Enable state, programmingremains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCCpower is removed from the (ERASE): The Erase (ERASE) instruction programs all bits in the specifiedmemory location to the logical “1” state. The self-timed erase cycle starts once theERASE instruction and address are decoded. The DO pin outputs the READY/BUSYstatus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).A logic “1” at pin DO indicates that the selected memory location has been erased, andthe part is ready for another (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to bewritten into the specified memory location. The self-timed programming cycle, tWP, startsafter the last bit of data is received at serial data input pin DI. The DO pin outputs theREADY/BUSY status of the part if CS is brought high after being kept low for a minimum53408C–SEEPR–1/04元器件交易网 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic“1” indicates that the memory location at the specified address has been written with thedata pattern contained in the instruction and the part is ready for further instructions. AREADY/BUSY status cannot be obtained if the CS is brought high after the end ofthe self-timed programming cycle, ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-ory array to the logic “1” state and is primarily used for testing purposes. The DO pinoutputs the READY/BUSY status of the part if CS is brought high after being kept low fora minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locationswith the data patterns specified in the instruction. The DO pin outputs the READY/BUSYstatus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).The WRAL instruction is valid only at VCC = 5.0V ± 10%.

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, theErase/Write Disable (EWDS) instruction disables all programming modes and should beexecuted after all programming operations. The operation of the READ instruction isindependent of both the EWEN and EWDS instructions and can be executed at anytime.6AT93C86A [Preliminary]3408C–SEEPR–1/04元器件交易网93C86A [Preliminary]Timing DiagramsSynchronous Data TimingNote: is the minimum SK zation Key for Timing DiagramsAT93C86A (16K)I/OANDNx 8A10D7x 16A9D1573408C–SEEPR–1/04元器件交易网D TimingtCSHigh 8AT93C86A [Preliminary]3408C–SEEPR–1/04元器件交易网93C86A [Preliminary]WRITE Timing