Count < NmaxNoYesAdderd < d + T2NmaxmPath Metric 2NmaxNoDiscard pathT = T − tofadaptiveViterbidecoderoftheAVAdecoderisthesame,thisearlierworpre-viousAVAapproaches[2],thestandardoperationofeliminatingthelargest-metricpathwhentwosurvivorpathsenterthesametrellisstatewasnotimplemenlementedalgorithmmorecloselyre-semblesapredecessoroftheAVAknownastheSimmonsT-algorithm[3].HITECTUREToexplorethepowerbenefichitectureexhibitssig-nificantparallelismandsupportsdynamicreconfiguratrereconfi-levelviewofthstViterbidecoders[11],thedat-apathissplitintofourparts:thebranchmetricgenerators(BMG),add-compare-select(ACS)units,thesurvivormemoryunit,unitdeterminespathcostsandidentifivivormemorystoreslowestcostbit-sequencepathsbasedondecisionsflowofdatatinctivefeaturesofourdecoderaretheparalmplementeddecoder,theexpectedsymbolvalue(BMselect)isusedtoselecttheappropriatebranchmetricfromtheBMG,anchmetricvalueiscombinedwiththepathmetricofitsparentpresentstatetoformanewpathmetric,trellisstage,theminimum-valuesurvivingpathmetricamongallpathmetricsfortheprecedingtrellisstage,dm,hmetricsarecomparedtothesumdm+atorsarethenusedtodeterminethelifeofeachpathbasedonthethreshold,hresholdconditionisnotsatisfiedbypathmetricdm+T,epathsthatmeetthethresholdconditionaredetermined,gcircuitryiseliminatedbyumberofpathsthatsurvivethethresholdislessthanNmax,inFigure2,forstageswhenthenumberofpathssurvivingthethresholdconditionisgreaterthanNmax,Tisiterativelyreducedby2forthecurrenttrellisstageuntilthenumlueisrriatevaluesforTandNmaxweredeterminedinpreviouswork[8],sothatTreductionisneededinfrequently(forlessthan5%ofsymbols).TheoutputoftheACSunitsincludespathvalidsignalswhichindicatewhichofthe2*sregardingotherdecodercomponentscanbefoundin[8].Mostcommunicationsystemsdesirelinkswithpredictableperfor-mance,whichisusuallyspecifiedbyafighdesireddecoderaccuracyremainsconstant,channelsignal-to-noiseratioscanvarywidelyduetofactorssuchasthepropagaresenceofincreasednoisepower(equivalently,adecreasedSNRduetoaweakersignal),beshowninSectionV,AVAdecodersforhigherconstraint-lengthcodesrequirealargeramountoflogicresourcesandcncoderanddecoderhardwarecanbereconfiguredtoexactlymatchtheconstraintlengthrequiredataspecifictimeinstant,resenceofincreasednoise,ahigh-constraintlengthencoderanddecoder(largerK)oisepowerisreduced,alow-constraintlengpingisnotallowed,hannelnoisestatisticsdonotgenerallychangeinstantaneously,reconfigurationbasedonchannelnoisestatisticscanbeperformedatacoarsetimescale,atformTotestthepracticalityofourreconfigurableAVAarchitecture,ahardwareidomBitGeneratorisaCmvolutionalencoder,ulatorconvertsacodedbittoarealnum-ber:0->1,1->-1forthebinaryphase-shiftkeyed(BPSK)system3 BitsRandom

Bit GeneratorConvolutionalEncoderBitsModulatorFloatingPointAWGNChannelModelFloatingPoint3−bit quantizerInputSequenceOutputSequenceBitsAdaptiveViterbiDecoderOn FPGAK456789101112Nmax478889212525T8202323TL205560XC4036XL-08CLBsFFs553278847881296820NANANANANANAXCV1000-04CLBSlicesFFs4362789225475686432CompareOn ocksimulabolsobtainedfromtheAWivingtheinput,twaremoreImplementationTheAVAdecoderarchitecturewasmappedtoaXilinxXC4036XL-08FPGAlocatedonanAnnapolisMicroSystemsWildOneboard[12].Thismappingallowedforin-fieldtestingofAVAdesignsforconstraintlengthsuptoK=eveldescriptionoftheadaptLcodewassimulatedusingCadenceAffi-signsweresynthesizedusingSynratingfrequonsumptionvaluesfortheAVAdecodersimplementedintheXC4036XLweredeterminedwiththefollowingequationfrom[12]:Power=((0.02∗f)+0.09)∗A∗V(1)wherefisthedesignfrequency,AisthepercentageofuseddeviceflipflopsandI/Osmultipliedbytheirswitchingactivity,hingactivityof30%[13]untforpowerconsumptionduringXC4036XLreconfiguration,thepowerassociatedwithreadingtheconfieterminedthatapproximately5mWofpowerareneededdur-ingreconfigurationtoreadthe832,480XC4036XLconfigurationbitsfrom2Mx32MicronMT48LC2M32B2SDRAM[14].Thisvaluewasdeterminedbyscalingthespecifiedmaximumpowerdissipationat200MHzbytherequired4MHzFPGAconfiuntofpowerrequiredtoreconfiguretheXC4036XLusingtheon-chipre-configurationshiftchainwasdeterminedbycalculatingtheenergydis-sipatedbyasinglechainshiftin0.35µluewasscaledbytherequired832,480shiftsanddividedbyconfig-urationtimetocalculateFPGAreconfialcu-latedthat1.9mWarerequiredtoreprogramtheconfiC4036XLreconfigurationtimeis40ms[15].14412470NANA67412446TABLEIFPGARESOURCEUTILIZATIONFORTHEADAPTIVEVITERBIDECODERFORBEROF10−5TotestlargerAVAimplementations,decoderswithconstraintlengthsuptoK=ghtheXCV1000designswerenotphysicallyimplementedinhardware,cycleperiodsfromTRACEwereusedinconsumptionvaluesfortheAVAdecodersmappedtotheXCV1000weredeterminedusingtheXilinxXPowertool[16].Thesevaluesandaswitchingactivityvalueof30%wereeterminedthatapproximately62.5mWofpowerareneededduringreconfigura-tiontoreadthe6,127,744XCV1000configurationbitsfrom2Mx32MicronMT48LC2M32B2SDRAM[14].Thisvaluewasdeterminedbyscalingthespecifiedmaximumpowerdissipationat200MHzbytherequired50MHzFPGAconfiuntofpowerrequiredtoreconfiguretheXCV1000usingtheon-chipreconfigura-tionshiftchainwasdeterminedbycalculatingtheenergydissipatedbyasinglechainshiftin0.22µluewasscaledbytherequired6,127,744shiftsanddividedbyconfigura-tiontimetocalculateFPGAreconfialculatedthat27.4mWarerequiredtoreprogramtheconfiCV1000reconfigurationtimeis15.3ms[17].sourceUsageandNon-ReconfigurablePerformanceThelogicresourcesusedbytheadaptiveViterbidecoderarchitec-turedescribedinSectionIIIwasmeasuredintermsoflogicblock(CLB)summarizestheresourceutilizationoftheadap-tiveViterbidecoderonanXC4036XLforconstraintlengthsK=4to9andonanXCV1000forconstraintlengthsK=tiveViterbidecoderwithK=9utilized100%ofXC4036CLBresources(85%LUTutilization),whileaK=14AVAdecoderfitsinasingleXCV1000device(52%LUTutilization).FortheAVAhardware,im-plementationsizeisaffectedbyTviathecomparisonbetweenpathcosts,diandthesumdm+mvaluesofTrangebetween14and24,asdeterminedin[8]henumberofcomparatorsisdirectlyrelatedtoNmax,electedtobeoptimal,communicationsystems,bothdecoderateandmaximumBERarefifollowedtheninTableII,duetoanincreaseinrequiredcyclesperdecodedbitandincreasedcriticalpathlength,maximumdecodeDecodeRate-105.9KbpsMaxDecodeRateKXC4036XLSNRPowerXC4036XLSA-1100clockrange(mW)(Kbps)(Kbps)(MHz)(dB)412.96.3-6.545.7333.722.2513.06.1-6.356.2164.217.4613.05.5-6.179.8162.310.3713.03.9-5.5125.1160.89.4813.03.7-3.9130.4143.68.7913.03.1-3.7135.7141.17.0TABLEIIPERFORMANCEANDPOWERCONSUMPTIONFORAXC4036XL-08ANDASTRONGARMSA-1100ATABEROF10−Rate-61.7KbpsMaxDecodeRateKXCV1000SNRPowerXCV1000clockrange(mW)(Kbps)(MHz)(dB)47.56.3-6.5241415.057.56.1-6.3287303.267.55.5-6.1319300.077.53.9-5.5331283.687.63.7-3.9336277.997.63.1-3.7339240.31015.53.0-3.1853101.51216.12.8-3.093794.91417.22.5-2.8161182.3TABLEIIIPERFORMANCEANDPOWERCONSUMPTIONFORAXCV1000-04ATABEROF10−pault,forouranalysisthefixeddecoderateofalldecodersissettobe75%ofthemaximumdecoderateoftheK=9de-coder(105.9Kbps).This25%rateoverheadissufficienttoaccountfornon-infiAclockratesrequiredtoachievethisficolumninthetableindicatestherangeofchannelnoisestatisticsoverwhichagivendecoderistheminimumconstraintlengthdecoderthatachievesthetargetBERof10−mn4ofTableII,forafixeddecoderate,decoderpowerconsumptionarisontoanXC4036XLimplementation,themaximumpos-sibledecoderateofasoftwareAVAimplementationona206MHzStrongARMSA-1100microprocessorisnearly5×slowerthanthede-sired105.9Kbpsrate(TableII).Additionally,SA-1100powervalues,calculatedwithJouleTrack[18],rangebetween350and400mWfortheconstraintlengthslistedinTableII,morethan2×-1100isimplementedinthesametechnology(0.35µm)astheXC4036XL-08andusesalowersupplyvoltage(1.5Vversus3.3V).TableIIIsummarizestheperformanceandpowerdissipatedbyAVAdecodersintheXCV1000-04FPGAforafiexperiment,thefixeddecoderateissetto61.7Kbps,75%ofthemax-imumK=eXC4036XLdecoders,powerconsumptionincreaseswithincreasedK,asBERanddecoderateremainsficReconfigurationInthesecondsetofexperiments,channelnoise,asindicatedbySNR,wasusedtoindicatewhentheencoderanddecodercouldbere-configuredtomatchafixedBERof10−avingsisachievedbyusingalowerconstraintlengthencoderand,hence,lowerconstraintlengthandlower-powerdecoderforhighSNR,andahigherconstraintlengthencoderand,hence,valuations,itisassumedthatthecurrentchannelSNRedbackofthepath-lossandshadowingiscommonlydoneinmodernwirelesscommunicationsystems[4].ExperimentsrequiringreconfigurationoftheXC4036XLwereper-formedbyvaryingtheSNRoftransmitteddataandreconfiguringtheAVAhardwarebasedon(K,Nmax)10,000SNRsweregeneratedusingalog-normalshadowingdistribution[1]ntheassump-tionthatSNRcanbesampledsuccessfullyevery250,000bits[1],FPGAhardwarewasperiodicallyreconfilSNRvalueswerevariedbetween3.1and6.5dB(requiringKvaluesbetween4and9)andAVAconfierconsumptionforadynamically-reconfiguredversusastaticXC4036XLdecoderforafixeddecoderate(105.9Kbps)andBER(10−5)generatedsetofSNRs,FPGAreconfigurationwasperformed7065outof10,000possibletimesleadingtoatotalreconfitainadecoderateof105.9Kbpswhiletakingintoaccountthe282.6secondsofdecodeinactivity,eachindividualdecoderwasrunataclockrate2%staticdecodercase,aK=ofdynamicreconfigurationleadstoa27%efitsofcoarse-graineddynamicreconfigurationforacon-straintlengthofK=lSNRvalueswerevariedbetween2.5and6.5dB,requiringKvaluesbetween4and14andAVAconfigeneratedsetofSNRs,FPGAreconfigurationwasperformed7007outof10,000possibletimeslead-ingtoatotalreconfitainade-coderateof61.7Kbpswhiletakingintoaccountthe107.2secondsofdecodeinactivity,eachindividualdecoderwasrunataclockrate1%nfigurationisnotused,astatic,K=14,ofdynamicreconfigurationleadstoa69%parentthatasabroaderrangeofconstraintlengthsisconsidered,theamountofpossiblepowersavingsduetodynamicreconfiSIONANDFUTUREWORKTheuseoferror-correctingcodeshasproventobeaneffmanuscript,apower-effiureitspowerconsumption,theAVAarchitecturehasbeenimplementeven,fixedbit-erroranddecoderate,powersavingsisachievedbyadaptingthecon-straintlengthoftheconvolutionalcodeemployed,(Kbps)XC4036XL-08Static105.9Dynamic105.9XCV1000-04Static61.7Dynamic61.7Decodetime(sec)236140521Reconfied(outof10,07TABLEIVReconfiad(sec)(mW)135.798.81611.0505.3[15]XilinxXC4000DataSheet,XilinxCorporation,2001,.[16]ISEManual,XilinxCorporation,2001,.[17]XilinxVirtexDataSheet,XilinxCorporation,2001,.[18]akasan,“JouleTrack-awebbasedtoolforsoft-wareenergyprofiling,”inProceedings,ACM/IEEE35rdDesignAutoma-tionConference,June2001,pp.220–DECODERVERSUSDYNAMICALLY-RECONFIGURABLEDECODERPOWERCONSUMPTIONconfigurableFPGAimplementationisshowntoconsumesignifiuture,weplantoconsiderthedecodingbenefihtintegrationofsequentialcontrolwithparalleldecodingmayprovidefurtherrun-timepowerbenefiLEDGMENTSThisworkwassponsoredbyNationalScienceFoundationgrantsCCR-0081405,CCR-9988238,horswishtothankFrankHonor´NCES[1]s,k,N.Y.:McGraw-Hill,1995.[2]n,“AdaptiveViterbidecodingofconvolutionalcodesovermemorylesschannels,”IEEETransactiononCommunica-tions,vol.45,no.11,pp.1389–1400,Nov.1997.[3]s,“Breath-firsttrellisdecodingwithadaptiveeffort,”IEEETransactionsonCommunications,vol.38,no.1,pp.3–12,Jan.1990.[4],andran,,“Adaptationtechniquesinwirelesspacketdataservices,”IEEECommunicationsMagazine,vol.38,no.1,pp.54–64,Jan.2000.[5],“Variable-complexitytrellisdecodingofbinaryconvolutionalcodes,”IEEETransactionsonCommunications,vol.44,no.2,pp.121–126,Feb.1996.[6]s,“Anerrorboundforreduced-stateViterbidecodingofTCMcodes,”IEEECommunicationsLetters,vol.3,no.9,pp.266–268,Sept.1999.[7],“Sequentialcodingalgorithms:Asurveyandcostanalysis,”IEEETransactionsonCommunications,vol.32,no.2,pp.169–176,Feb.1984.[8]athan,r,l,on,“Ady-namicallyreconfigurableadaptiveViterbidecoder,”inProceedings,ACM/SIGDAInternationalSymposiumonFieldProgrammableGateAr-rays,Monterey,CA,Feb.2002,pp.227–236.[9]barti,“Lowpowerapproachtodecodingcon-volutionalcodeswithadaptiveViterbialgorithmapproximations,”inPro-ceedings,IEEE/ACMInternationalSymposiumonLowPowerElectron-icsandDesign,Monterey,CA,Aug.2002,pp.68–71.[10],,,,“AnadaptiveViterbialgorithmbasedonstronglyconnectedtrellisdecoding,”inProceedings,IEEEInternationalSymposiumonCircuitsandSystems,Scottsdale,AZ,May2002,pp.137–140.[11],“High-speedparallelViterbidecoding:Algo-rithmandVLSI-architecture,”IEEECommunicationsMagazine,vol.29,no.5,pp.46–55,May1991.[12]WILD-ONEReferenceManual,AnnapolisMicrosystems,Inc.,1999.[13],i,a,“DynamicpowerconsumptioninVirtex-IIFPGAfamily,”inProceedings,ACM/SIGDAInternationalSym-posiumonFieldProgrammableGateArrays,Monterey,Ca.,Feb.2002,pp.157–164.[14]MT48LC2M32B2SDRAMDataSheet,MicronTechnologies,Inc.,2003.