2023年6月24日发(作者：)

BDTIC /es•Medium-voltage and Standard-voltage Operation–2.7 (VCC = 2.7V to 5.5V)•Automotive Temperature Range –40°C to +125°C•User Selectable Internal Organization–16K: 2048 x 8 or 1024 x 16•3-wire Serial Interface•Sequential Read Operation•Schmitt Trigger, Filtered Inputs for Noise Suppression•2 MHz Clock Rate (5V) Compatibility•Self-timed Write Cycle (10 ms max)•High Reliability–Endurance: 1 Million Write Cycles–Data Retention: 100 Years•Lead-Free/Halogen-Free Devices Available•8-lead JEDEC SOIC and 8-lead TSSOP ptionThe AT93C86A provides 16384 bits of serial electrically erasable programmable readonly memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pinis connected to VCC and 2048 words of 8 bits each when it is tied to ground. Thedevice is optimized for use in many automotive applications where low-power andlow-voltage operations are essential. The AT93C86A is available in space saving 8-lead JEDEC SOIC and 8-lead TSSOP ConfigurationPin NameFunction8-lead SOICCSChip SelectCS18VCCSKSerial Data ClockSK27DCDISerial Data InputDI36ORGDOSerial Data OutputDO45GNDGNDGroundVCCPower Supply8-lead TSSOPORGInternal OrganizationDCDon’t ConnectCS18VCCSK27DCDI36ORGDO45GNDThe AT93C86A is enabled through the Chip Select pin (CS), and accessed via athree-wire serial interface consisting of Data Input (DI), Data Output (DO), and ShiftClock (SK). Upon receiving a Read instruction at DI, the address is decoded and thedata is clocked out serially on the data output pin DO. The write cycle is completelyself-timed and no separate erase cycle is required before Write. The write cycle is onlyenabled when the part is in the Erase/Write Enable state. When CS is brought “high”following the initiation of a write cycle, the DO pin outputs the Ready/Busy status ofthe part. The AT93C86A is available in a 2.7V to 5.5V version.

Three-wireAutomotive

Temperature

SerialEEPROM16K (2048 x 8 or 1024 x 16)AT93C86ARev. 5096E–SEEPR–1/08Absolute Maximum Ratings*–55°C to +125°.–65°C to +150°CVoltage on any Pinwith Respect –1.0V to +7.0VMaximum 6.25VDC 5.0 mA*NOTICE:Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only, and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device Diagram

VccGNDMEMORY ARRAYORG2048 x 8OR1024 x 16ADDRESSDECODERDATAREGISTERDIMODEDECODELOGICOUTPUTBUFFERCSSKCLOCKGENERATORDONote:When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization

is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1

Meg ohm pullup, then the x 16 organization is Capacitance(1)Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)SymbolCOUTCINNote:Test ConditionsOutput Capacitance (DO)Input Capacitance (CS, SK, DI) parameter is characterized and is not 100% 55UnitspFpFConditionsVOUT = 0VVIN = 0V2AT93C86A5096E–SEEPR–1/08AT93C86ATable CharacteristicsApplicable over recommended operating range from: TA =

–40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwisenoted)SymbolVCC1VCC2ICCISB1ISB2IILIOLVIL1(1)VIH1(1)VOL1VOH1Note:ParameterSupply VoltageSupply VoltageSupply CurrentStandby CurrentStandby CurrentInput LeakageOutput LeakageInput Low VoltageInput High VoltageOutput Low VoltageOutput High VoltageVCC = 5.0VVCC = 2.7VVCC = 5.0VREAD at 1.0 MHzWRITE at 1.0 MHzCS = 0VCS = 0VTest ConditionMin2.74.50.50.56.010.0TypMax5.55.52.02.010.015.03.03.00.8VCC + 10.42.4UnitVVmAmAµAµAµAµAVVVVVIN = 0V to VCC 0.1VIN = 0V to VCC 0.12.7V ≤ VCC ≤ 5.5VIOL = 2.1 mAIOH = –0.4 mA−−−−0.62.02.7V ≤ VCC ≤ min and VIH max are reference only and are not CharacteristicsApplicable over recommended operating range from TA

= –40°C to +125°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted)SymbolfSKtSKHtSKLtCStCSStDIStCSHtDIHtPD1tPD0ParameterSK Clock

FrequencySK High TimeSK Low TimeMinimum CS

Low TimeCS Setup TimeDI Setup TimeCS Hold TimeDI Hold TimeOutput Delay to ‘1’Output Delay to ‘0’Test Condition4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5VRelative to SKRelative to SKRelative to SKRelative to SKAC TestAC Test4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5VMin525TypMax21UnitsMHznsnsnsnsnsnsnsnsns35096E–SEEPR–1/08Table Characteristics (Continued)Applicable over recommended operating range from TA

= –40°C to +125°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted)SymboltSVtDFtWPEndurance(1)ParameterCS to Status ValidCS to DO in High

ImpedanceWrite Cycle Time5.0V, 25°CTest ConditionAC TestAC TestCS = VIL4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V4.5V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V2.7V ≤ VCC ≤ 5.5V0.11M4MinTypMax25UnitsnsnsmsWrite CyclesNote: parameter is characterized and is not 100% tested.

Table ctionREADEWENERASEWRITEERALWRALInstruction Set for the AT93C86AAddressSB111111Op Code1x 8A10 – A011XXXXXXXXXA10

– A0A10 – A010XXXXXXXXX01XXXXXXXXXx 16A9 – A011XXXXXXXXA9

– A0A9

– A010XXXXXXXX01XXXXXXXXD7 – D0D15

– D0D7

– D0D15

– D0x 8Datax 16CommentsReads data stored in memory,

at specified enable must precede all

programming memory location An – memory location An – all memory locations.

Valid only at VCC = 4.5V to all memory locations.

Valid when VCC = 4.5V to 5.5V and

Disable Register es all programming

10000XXXXXXXXX00XXXXXXXX4AT93C86A5096E–SEEPR–1/onal DescriptionThe AT93C86A is accessed via a simple and versatile 3-wire serial communication operation is controlled by seven instructions issued by the host processor. A validinstruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by theappropriate Op Code and the desired memory address (READ): The Read (READ) instruction contains the address code for the memory loca-tion to be read. After the instruction and address are decoded, data from the selected memorylocation is available at the serial output pin DO. Output data changes are synchronized with therising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or16-bit data output string. The AT93C86A supports sequential read operations. The device willautomatically increment the internal address pointer and clock out the next memory location aslong as CS is held high. In this case, the dummy bit (logic “0”) will not be clocked out betweenmemory locations, thus allowing for a continuous stream of data to be /WRITE (EWEN): To assure data integrity, the part automatically goes into theErase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)instruction must be executed first before any programming instructions can be carried note that once in the EWEN state, programming remains enabled until an EWDS instruc-tion is executed or VCC power is removed from the (ERASE): The Erase (ERASE) instruction programs all bits in the specified memorylocation to the logical “1” state. The self-timed erase cycle starts once the Erase instruction andaddress are decoded. The DO pin outputs the Ready/Busy status of the part if CS is broughthigh after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that theselected memory location has been erased, and the part is ready for another (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be writteninto the specified memory location. The self-timed programming cycle tWP starts after the last bitof data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of thepart if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DOindicates that programming is still in progress. A logic “1” indicates that the memory location atthe specified address has been written with the data pattern contained in the instruction and thepart is ready for further instructions. A Ready/Busy status cannot be obtained if the CS isbrought high after the end of the self-timed programming cycle ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory arrayto the logic “1” state and is primarily used for testing purposes. The DO pin outputs theReady/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns(tCS). The Eral instruction is valid only at VCC = 5.0V ± 10%.

WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with thedata patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part ifCS is brought high after being kept low for a minimum of 250 ns (tCS). The Wral instruction isvalid only at VCC = 5.0V ± 10%.

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, theErase/Write Disable (EWDS) instruction disables all programming modes and should be exe-cuted after all programming operations. The operation of the Read instruction is independent ofboth the Ewen and Ewds instructions and can be executed at any time.55096E–SEEPR–1/ DiagramsFigure onous Data TimingNote: is the minimum SK zation Key for Timing DiagramsAT93C86A (16K)I/OANDNx 8A10D7x 16A9D15Figure Timing6AT93C86A5096E–SEEPR–1/08AT93C86AFigure Figure Figure Timing