2023年6月24日发(作者：)

Section III: Platform Boot, Control, and StatusChapter 16: Boot ModesIn the eMMC1 boot mode, the RCU BootROM runs at an eMMC1 device clock frequencybetween 8.7 MHz and 19.3 MHz dependent on the REF_CLK setting. The eMMC1 boot modesupports 1.8V and 1-bit, 4-bit, and 8-bit data interfaces. The BootROM uses auto-widthdetection to determine the data bus width for initial boot. The auto-bus width detection starts bychecking the 8-bit data bus width, followed by 4-bit data bus width, and then 1-bit data : When connecting to the eMMC1 controller using a 1-bit data bus width, note the detection orderbecause the remainder of the 8-bit data bus MIO data pins toggle during the initial bus-width additional information on the SD/eMMC controller, see SD/eMMC 1 SignalsIn eMMC1 boot mode, the MIO[0, 3:12] are configured by the BootROM to use:•Default drive strength (8 mA)•Default slew rate (slow)•Default weak pull-ups (enabled)•Enables the Schmitt trigger•Disables the 3-state overrideThe remaining MIOs are not set by the BootROM and remain at their default state. If a securelockdown occurs during boot, the BootROM sets the to 0xFFFFFFFF to 3-state all I/Os. SeeVersal ACAP Register Reference (AM012) for following table lists the bidirectional PMC multiplexed I/Os (MIOs) and their functions usedin the eMMC1 boot mode 23: eMMC1 Boot Mode SignalsPMC MIO PinSignal Name12EMMC1_CLKEMMC1_CMDeMMC1 clock outputeMMC1 commandDescriptionEMMC1_DATA[0]Data pin used in eMMC1 boot mode (1-bit, 4-bit, 8-bit)EMMC1_DATA[1]Data pin used in eMMC1 boot mode (4-bit, 8-bit)EMMC1_DATA[2]Data pin used in eMMC1 boot mode (4-bit, 8-bit)EMMC1_DATA[3]Data pin used in eMMC1 boot mode (4-bit, 8-bit)EMMC1_DATA[4]Data pin used in eMMC1 boot mode (8-bit)EMMC1_DATA[5]Data pin used in eMMC1 boot mode (8-bit)EMMC1_DATA[6]Data pin used in eMMC1 boot mode (8-bit)EMMC1_DATA[7]Data pin used in eMMC1 boot mode (8-bit)EMMC1_RSTReset output that resets the eMMC flashAM011 (v1.1) November 30, 2020Versal ACAP TRMSection III: Platform Boot, Control, and StatusChapter 16: Boot ModeseMMC1 InterfaceThe following figure shows an example setup for eMMC1 boot mode from a single flash 26: eMMC1 Interface ExampleVersal Device

MODE[3:0]REF_CLKPOR_BDONEERROR_OUTPMC Dedicated I/O BankeMMC Device

EMMC1_CLKEMMC1_CMDEMMC1_DATA[7:0]EMMC1_RSTCLKCMDDAT[7:0]RESET

0110REF_CLKPOR_BDONE StatusERROR_OUT StatusPMC MIO Bank 0X22630-102020Octal SPI Boot ModeThe octal SPI (OSPI) boot mode has an SPI compatible serial bus interface with extended octalcommands. The OSPI boot mode supports an 8-bit data bus width and single transfer rate (STR)during the RCU BootROM execution. The BootROM runs at an OSPI device clock frequencybetween 11 MHz and 24.5 MHz dependent on the REF_CLK setting. After the BootROMexecution, the PLM can support the double data rate (DDR) with strobe for higher OSPI boot mode can be configured to a OSPI single or dual-stacked setup. For additionalinformation on the OSPI controller, see Octal SPI : When using OSPI dual-stacked mode, the BootROM can only access the lower OSPI0 addressableflash memory space for boot. After boot, the PLM can access the upper OSPI1 for additional following table lists the STR OSPI commands supported by the RCU 24: OSPI Commands Supported by RCU for BootBoot ModeOSPIOSPIData Width11Read CommandRead4-byte readCommand Code03h13hDummy Cycles--AM011 (v1.1) November 30, 2020Versal ACAP TRMSection III: Platform Boot, Control, and StatusChapter 16: Boot ModesTable 24: OSPI Commands Supported by RCU for Boot (cont'd)Boot ModeOSPIData Width8Read Command4-byte octal output fast readCommand Code7ChDummy Cycles8In OSPI boot mode, the device initiates the boot sequence with the default 4-byte address octaloutput fast read command code 7Ch and the BootROM searches for a valid boot header. If avalid boot header is not found, the Versal ACAP attempts to load the image using the 4-bytealternate addressing read command code 13h. If a valid boot header is still not detected, thebasic read command 03h is tried. If the boot attempt is unsuccessful after the third command,the BootROM increments the image header address register by 32 KB and tries the OSPIcommand sequence again to locate a valid boot header. If the OSPI boot mode search limit isreached without a successful boot, the RCU goes into lockdown and the ERROR_OUT pin is image search limit for each boot mode is listed in Table 15: Boot Mode Search SPI SignalsIn OSPI boot mode, MIO[0:5, 7:12] are configured by the BootROM to use:•Default drive strength (8 mA)•Default slew rate (slow)•Default weak pull-ups (enabled)•Enables the Schmitt trigger•Disables the 3-state overrideThe remaining MIOs are not set by the BootROM and remain at their default state. If a securelockdown occurs during boot, the BootROM sets the to 0xFFFFFFFF to 3-state all I/Os. SeeVersal ACAP Register Reference (AM012) for following table lists the bidirectional PMC multiplexed I/Os (MIOs) and their functions usedin the OSPI boot mode 25: Octal SPI Boot Mode SignalsPMC_MIO PinSignal Name012345OSPI_CLKOSPI_IO[0]OSPI_IO[1]OSPI_IO[2]OSPI_IO[3]OSPI_IO[4]DescriptionOSPI clock output for OSPI0 in single setup, or OSPI clock output for OSPI0 and OSPI1in dual-stacked pin used for OSPI single or dual-stacked boot mode setupData pin used for OSPI single or dual-stacked boot mode setupData pin used for OSPI single or dual-stacked boot mode setupData pin used for OSPI single or dual-stacked boot mode setupData pin used for OSPI single or dual-stacked boot mode setupAM011 (v1.1) November 30, 2020Versal ACAP TRM