2024年4月11日发(作者：)

专利内容由知识产权出版社提供

专利名称：MANUFACTURE OF SEMICONDUCTOR

INTEGRATED CIRCUIT DEVICE AND

SEMICONDUCTOR MANUFACTURING

DEVICE

发明人：IRIKITA NOBUYUKI,入来 信行,TANIGUCHI

YUZO,谷口 雄三,KUNIYOSHI SHINJI,国吉 伸

治,KATO TAKESHI,加藤 毅,HIRANUMA

MASAYUKI,平沼 雅幸,MATSUMOTO HIDEYA,

松本 秀也,NAKADA MASAHIKO,中田 匡

彦,NAMIKI YOSHIJI,南木 美嗣,HOSOE

TAKURO,細江 卓朗,IKUMI MASUZO,生見 益三

申请号：JP特願平4-250328

申请日：19920921

公开号：JP特開平6-104156A

公开日：19940415

专利附图：

摘要：PURPOSE:To improve alignment accuracy between a plurality of circuit pattern

layers previously formed on a semiconductor substrate and a circuit pattern layer to be

transcribed by knowing an actual alignment error generated between a plurality of circuit

pattern layers on a semiconductor substrate and a reference layer by data of a third

polygon. CONSTITUTION:An alignment shear amount between a reference layer on a

semiconductor water and a plurality of circuit pattern layers previously formed on a

semiconductor water, and an alignment shear amount between the reference layer and a

specified circuit pattern layer to be transcribed are measured by using an alignment

accuracy pattern to obtain two-dimensional distributions 7a to 7c of alignment shear.

Successively, the tow-dimensional distributions 7a to 7c of the alignment shear are

estimated by projecting polygons 7a1 to 7c1 to grasp the state of actual alignment shear

and to obtain a correction amount of alignment of an exposure treatment part. Thereby,

it is possible to improve alignment accuracy and to improve manufacturing yield and

reliability of a semiconductor integrated circuit device.

申请人：HITACHI LTD,株式会社日立製作所,HITACHI ELECTRON ENG CO LTD,日立電子エン

ジニアリング株式会社

地址：東京都千代田区神田駿河台四丁目6番地,東京都千代田区大手町2丁目6番2号

国籍：JP,JP

代理人：筒井 大和

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