2023年8月2日发(作者：)

专利内容由知识产权出版社提供专利名称：Semiconductor memory device including aboost potential generation circuit发明人：Kaneko, Tetsuya, c/o Int. Prop. Div. a,Ohsawa, Takashi, c/o Int. Prop. Div.K.K. Toshiba申请号：EP94120821.7申请日：19941228公开号：EP0661710A2公开日：19950705专利附图：摘要：A semiconductor integrated circuit device comprises a boost potentialgeneration circuit (24), word line drive system circuit (25), refresh cycle select circuit (21),word line system boost potential control circuit (22) and boost potential generationsystem control circuit (23). The boost potential generation circuit (24) steadily generatesa higher boost potential (φ3) than an externally applied voltage. The word line drivesystem circuit (25) delivers the boost potential (φ3), as a power supply, from the boostpotential generation circuit (24) so as to drive the corresponding word line. The word linesystem boost potential control circuit (22) sets at a substantially constant level a boostpotential output from the boost potential generation circuit (24). The boost potentialgeneration system control circuit (23) receives a designation signal (φ4) from the refreshcycle select circuit (21) so as to designate a refresh cycle and supplies a control signal(φ2A-1 to φ2A-n), which is generated based on the designation signal (φ4), to the boostpotential generation circuit (24), whereby, when more word lines are driven at a time bythe word line system drive circuit (25), a current supply capability of the boost potentialgeneration circuit (24) is increased and, when less word lines are driven at a time, thecurrent supply capability of the boost potential generation circuit (24) is decreased.申请人：KABUSHIKI KAISHA TOSHIBA地址：72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP国籍：JP代理机构：Lehn, Werner, Dipl.-Ing.更多信息请下载全文后查看