2023年6月24日发(作者：)

25LC010A25LC020A25LC040A1K-4K SPI Serial EEPROM High Temp Family Data SheetFeatures:•Max. Clock 5 MHz•Low-Power CMOS Technology:-Max. Write Current: 5 mA at 5.5V, 5 MHz-Read Current: 5 mA at 5.5V, 5 MHz-Standby Current: 10 μA at 5.5V•128 x 8 through 512 x 8-bit Organization•Byte and Page-level Write Operations•Self-Timed Erase and Write Cycles (6 ms max.)•Block Write Protection:-Protect none, 1/4, 1/2 or all of array•Built-in Write Protection:-Power-on/off data protection circuitry-Write enable latch-Write-protect pin•Sequential Read•High Reliability:-Endurance: >1M erase/write cycles-Data retention: > 200 years-ESD protection: > 4000V•Temperature Range Supported:-Extended (H):-40°Cto+150°C•Package is Pb-Free and RoHS CompliantDescription:Microchip Technology Inc. 25LCXXXA* devices arelow-density 1 through 4 Kbit Serial Electrically Eras-able PROMs (EEPROM). The devices are organized inblocks of x8-bit memory and support the Serial Periph-eral Interface (SPI) compatible serial bus -level and page-level functions are bus signals required are a clock input (SCK) plusseparate data in (SI) and data out (SO) lines. Access tothe device is controlled through a Chip Select (CS)ication to the device can be paused via thehold pin (HOLD). While the device is paused, transi-tions on its inputs will be ignored, with the exception ofChip Select, allowing the host to service higher 25LCXXXA is available in a standard 8-lead SOICpackage. The package is Pb-free and e Types (not to scale)SOIC(SN)CSSOWPVSS12348765VCCHOLDSCKSIPin Function TableNameCSSOWPVSSSISCKHOLDVCCFunctionChip Select InputSerial Data OutputWrite-ProtectGroundSerial Data InputSerial Clock InputHold InputSupply Voltage*25LCXXXA is used in this document as a generic part number for the 25 series devices.© 2009 Microchip Technology inaryDS22136B-page 1/25LCXXXADevice Selection TablePart Number25LC010A25LC020A25LC040ADensity(bits)1K2K4KOrganization128 x 8256 x 8512 x 8VCC Range2.5V-5.5V2.5V-5.5V2.5V-5.5VMax. SpeedPage Size

(MHz)(Bytes)555161616Temp.

RangeHHHPackageSNSNSNDS22136B-page 2Preliminary© 2009 Microchip Technology :///25LCXXXA1.0ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings(†)6.5VAll inputs and -0.6V to VCC +1.-65°C to 155°CAmbient temperature .-40°C to 150°C(1)ESD protection on 4kVNote1:AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in whichthe total operating time between 125°C and 150°C will be greater than 1,000 hours is not warranted with-out prior written approval from Microchip Technology Inc.† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for anextended period of time may affect device 1-1:DC CHARACTERISTICSExtended (H):Min..7 VCC-0.3-0.3——VCC -0.5———TA = -40°C to +150°+10.3VCC0.2VCC0.40.2—±2±27UnitsVVVVVVμAμApFVCC ≥ 2.7VVCC < 2.7VIOL = 2.1mAIOL = 1.0mAIOH = -400μACS = VCC, VIN = VSS

OR VCCCS = VCC, VOUT = VSS

OR VCCTA = 25°C, CLK = 1.0MHz,VCC = 5.0V (Note)VCC = 5.5V; FCLK = 5.0MHz;

SO = OpenVCC = 2.5V; FCLK = 3.0MHz;

SO = OpenVCC = 5.5VVCC = 2.5VCS = VCC = 5.5V, Inputs tied to VCC or

VSS, 150°C VCC = 2.5V to 5.5VTest ConditionsDC 1VIL1VIL2VOLVOLVOHILIILOCINTCharacteristicHigh-level input

voltageLow-level inputvoltageLow-level outputvoltageHigh-level outputvoltageInput leakage currentOutput leakage

currentInternal Capacitance(all inputs and

outputs)D010ICC ReadOperating Current——52.5mAmAmAmAμAD011D012Note:ICC WriteICCSStandby Current————5310This parameter is periodically sampled and not 100% tested.© 2009 Microchip Technology inaryDS22136B-page 3/25LCXXXATABLE 1-2:AC CHARACTERISTICSExtended (H):Min.——1020304050——1050——0——460160—1,000,000TA = -40°C to +150°CMax.53—————————100100——————100160—80160————————6—UnitsMHzMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsms VCC = 2.5V to 5.5VTest Conditions4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V—4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V(Note1)(Note1)4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V——4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V(Note1)4.5V ≤ Vcc ≤ 5.5V (Note1)2.5V ≤ Vcc ≤ 4.5V (Note1)4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V4.5V ≤ Vcc ≤ 5.5V (Note1)2.5V ≤ Vcc < 4.5V (Note1)4.5V ≤ Vcc ≤ 5.5V2.5V ≤ Vcc < 4.5V(Note2)AC .1718192021FCLKTCSSTCSHTCSDTsuTHDTRTFTHITLOTCLDTCLETVTHOTDISTHSTHHTHZTHVTWC—CharacteristicClock FrequencyCS Setup TimeCS Hold TimeCS Disable TimeData Setup TimeData Hold TimeCLK Rise TimeCLK Fall TimeClock High TimeClock Low TimeClock Delay TimeClock Enable TimeOutput Valid from Clock

LowOutput Hold TimeOutput Disable TimeHOLD Setup TimeHOLD Hold TimeHOLD Low to Output

High-ZHOLD High to Output

ValidInternal Write Cycle TimeEnduranceE/W Page Mode, 25°C, VCC = 5.5V

Cycles(Note3)Note1:This parameter is periodically sampled and not 100% tested.2:TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycleis complete.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specificapplication, please consult the Total Endurance™ Model which can be obtained from our web site:22136B-page 4Preliminary© 2009 Microchip Technology :///25LCXXXATABLE 1-3:AC Waveform:

VLO = 0.2VVHI = VCC - 0.2V

VHI = 4.0V

CL = 50 pFTiming Measurement Reference LevelInputOutputNote1:For VCC ≤ 4.0V2:For VCC > 4.0V0.5 VCC0.5 VCC—(Note 1)(Note 2)—AC TEST CONDITIONS© 2009 Microchip Technology inaryDS22136B-page 5/25LCXXXAFIGURE 1-1:CS16SCK18SOn + 2n + 1nHigh-Impedance19n5nn - 1n - 1171617HOLD TIMINGDon’t CareSIHOLDn + 2n + 1nFIGURE 1-2:SERIAL INPUT TIMING4CS2Mode 1,1SCKMode 0,05SI6LSB in7831211MSB inSOHigh-ImpedanceFIGURE 1-3:SERIAL OUTPUT TIMINGCS9SCK13SOMSB outDon’t Care1415ISB out103Mode 1,1Mode 0,0SIDS22136B-page 6Preliminary© 2009 Microchip Technology :///25LCXXXA2.0PIN DESCRIPTIONS2.4Serial Input (SI)The SI pin is used to transfer data into the device. Itreceives instructions, addresses and data. Data islatched on the rising edge of the serial descriptions of the pins are listed in 2-1:NameCSSOWPVSSSISCKHOLDVCCPIN FUNCTION TABLEPin Number12345678FunctionChip Select InputSerial Data OutputWrite-Protect PinGroundSerial Data InputSerial Clock InputHold InputSupply Voltage2.5Serial Clock (SCK)The SCK is used to synchronize the communicationbetween a master and the 25LCXXXA. Instructions,addresses or data present on the SI pin are latched onthe rising edge of the clock input, while data on the SOpin is updated after the falling edge of the clock input.2.6Hold (HOLD)2.1Chip Select (CS)A low level on this pin selects the device. A high leveldeselects the device and forces it into Standby r, a programming cycle which is alreadyinitiated or in progress will be completed, regardless ofthe CS input signal. If CS is brought high during aprogram cycle, the device will go into Standby mode assoon as the programming cycle is complete. When thedevice is deselected, SO goes to the high-impedancestate, allowing multiple parts to share the same SPIbus. A low-to-high transition on CS after a valid writesequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequencebeing initiated.2.2Serial Output (SO)The HOLD pin is used to suspend transmission to the25LCXXXA while in the middle of a serial sequencewithout having to retransmit the entire sequence must be held high any time this function is not beingused. Once the device is selected and a serialsequence is underway, the HOLD pin may be pulledlow to pause further serial communication withoutresetting the serial sequence. The HOLD pin must bebrought low while SCK is low, otherwise the HOLDfunction will not be invoked until the next SCK high-to-low transition. The 25LCXXXA must remain selectedduring this sequence. The SI, SCK and SO pins are ina high-impedance state during the time the device ispaused and transitions on these pins will be ignored. Toresume serial communication, HOLD must be broughthigh while the SCK pin is low, otherwise serialcommunication will not resume. Lowering the HOLDline at any time will tri-state the SO SO pin is used to transfer data out of the25LCXXXA. During a read cycle, data is shifted out onthis pin after the falling edge of the serial clock.2.3Write-Protect (WP)The WP pin is a hardware write-protect input pin. Whenit is low, all write to the array or STATUS registers aredisabled, but any other operations function WP is high, all functions including nonvolatilewrites, operate normally. At any time, when WP is low,the write enable Reset latch will be reset and program-ming will be inhibited. However, if a write cycle isalready in progress, WP going low will not change ordisable the write cycle. See Table5-1 for Write-ProtectFunctionality Matrix.© 2009 Microchip Technology inaryDS22136B-page 7/25LCXXXA3.03.1FUNCTIONAL DESCRIPTIONPrinciples of OperationBLOCK DIAGRAMSTATUSRegisterHV GeneratorThe 25LCXXXA are low-density serial EEPROMsdesigned to interface directly with the Serial PeripheralInterface (SPI) port of many of today’s popular micro-controller families, including Microchip’s PIC® micro-controllers. It may also interface with microcontrollersthat do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match theSPI protocol.

The 25LCXXXA contains an 8-bit instruction device is accessed via the SI pin, with data beingclocked in on the rising edge of SCK. The CS pin mustbe low and the HOLD pin must be high for the 3-1 contains a list of the possible instructionbytes and format for device operation. All instructions,addresses, and data are transferred MSB first, (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25LCXXXA in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.I/O ControlLogicMemoryControlLogicXDecEEPROMArrayPage LatchesSISOCSSCKHOLDWPVCCVSSY DecoderSense Amp.R/W ControlTABLE 3-1:READWRITEWRDIWRENRDSRWRSRNote:INSTRUCTION SETInstruction FormatDescriptionRead data from memory array beginning at selected addressWrite data to memory array beginning at selected addressReset the write enable latch (disable write operations)Set the write enable latch (enable write operations)Read STATUS registerWrite STATUS register

Instruction Name0000 A80110000 A80100000 x1000000 x1100000 x1010000 x001For the 24LC040A device, A8 is the 9th address bit, which is used to address the entire 512 byte the 24LC020A and 24LC010A devcies, A8 is a don’t care.x = don’t 22136B-page 8Preliminary© 2009 Microchip Technology :///25LCXXXA3.2Read SequenceThe device is selected by pulling CS low. The 8-bitREAD instruction is transmitted to the 25LCXXXA fol-lowed by the 8-bit address. For the 25LC040A the MSb(A8) is sent to the slave during the instructionsequence. See Figure3-1 for more details. After thecorrect READ instruction and address are sent, the datastored in the memory at the selected address is shiftedout on the SO pin. The data stored in the memory at thenext address can be read sequentially by continuing toprovide clock pulses. The internal Address Pointer isautomatically incremented to the next higher addressafter each byte of data is shifted out. When the highestaddress is reached, the address counter rolls over toaddress 000h allowing the read cycle to be continuedindefinitely. The read operation is terminated by raisingthe CS pin (Figure3-1).tionally a page address begins with ‘XXXX 0000’ andends with ‘XXXX 1111’. If the internal address counterreaches ‘XXXX 1111’ and clock signals continue to beapplied to the ship, the address counter will roll back tothe first address of the page and over-write any datathat previously existed in those :Page write operations are limited to writingbytes within a single physical page,regardless of the number of bytesactually being written. Physical pageboundaries start at addresses that areinteger multiples of the page buffer size (or‘page size’) and, end at addresses that areinteger multiples of page size – 1. If a pagewrite command attempts to write across aphysical page boundary, the result is thatthe data wraps around to the beginning ofthe current page (overwriting datapreviously stored there), instead of beingwritten to the next page as might beexpected. It is therefore necessary for theapplication software to prevent page writeoperations that would attempt to cross apage boundary.3.3Write SequencePrior to any attempt to write data to the 25LCXXXA, thewrite enable latch must be set by issuing the WRENinstruction (Figure3-4). This is done by setting CS lowand then clocking out the proper instruction into the25LCXXXA. After all eight bits of the instruction aretransmitted, the CS must be brought high to set thewrite enable latch. If the write operation is initiatedimmediately after the WREN instruction without CSbeing brought high, the data will not be written to thearray because the write enable latch will not have beenproperly the write enable latch is set, the user mayproceed by setting the CS low, issuing a WRITE instruc-tion, followed by the 8-bit address, and then the data tobe written. Up to 16 bytes can be sent to the devicebefore a write cycle is necessary. The only restriction isthat all of the bytes must reside in the same page. Addi-For the data to be actually written to the array, the CSmust be brought high after the Least Significant bit (D0)of the nth data byte has been clocked in. If CS isbrought high at any other time, the write operation willnot be completed. Refer to Figure3-6 and Figure3-4for more detailed illustrations on the byte writesequence and the page write sequence, the write is in progress, the STATUS register maybe read to check the status of the WIP, WEL, BP1 andBP0 bits (Figure3-6). A read attempt of a memoryarray location will not be possible during a write the write cycle is completed, the write enablelatch is 3-1:CS0SCK1READ SEQUENCE2345678912223Instruction+Address MSbSI0000A801Lower Address Byte1A7A6A5A4A3A2A1A0Data Out76543210High-impedanceSOFor the 24LC010A device both A8 and A7 are don’t the 24LC020A device A8 is a don’t care.

© 2009 Microchip Technology inaryDS22136B-page 9/25LCXXXAFIGURE 3-2:CS0SCKInstruction+Address MSbSISO0000A801Lower Address Byte0A7A6A5A4A3A2A1A07High-impedance6Data Byte

543212223TwcBYTE WRITE SEQUENCEFor the 24LC010A device both A8 and A7 are don’t the 24LC020A device A8 is a don’t care.

FIGURE 3-3:CS0SCK12PAGE WRITE SEQUENCE345678912223Lower Address ByteData Byte 16543210Instruction+Address MSbSI0000A8010A7A6A5A4A3A2A1A07CS24252627282936373839SCKData Byte 2SI7654321076Data Byte 35432107Data Byte n (16 max.)6543210For the 24LC010A device both A8 and A7 are don’t the 24LC020A device A8 is a don’t care.

DS22136B-page 10Preliminary© 2009 Microchip Technology :/// 分销商库存信息:MICROCHIP25LC010A-H/SN25LC020AT-H/SN25LC010AT-H/SN25LC040A-H/SN25LC020A-H/SN25LC040AT-H/SN