2023年7月3日发(作者：)

SYNOPSYSVCS常⽤命令使⽤详解VCS对verilog模型进⾏仿真包括两个步骤：1. 编译verilog⽂件成为⼀个可执⾏的⼆进制⽂件命令为：vcs source_files

2. 运⾏该可执⾏⽂件：./simv类似于NC, 也有单命令⾏的⽅式：vcs source_files -R

-R 命令表⽰, 编译后⽴即执⾏。vcs常⽤的命令选项如下：

-cm line|cond|fsm|tgl|obc|path 　设定coverage的⽅式

+define+macro=value+ 　　　　　预编译宏定义

-f filename 　　　　　　　　　　　 RTL⽂件列表

+incdir+directory+ 　　　　　　　 添加include ⽂件夹

-I　　　　　　　　　　　　　　　　 进⼊交互界⾯

-l 　　　　　　　　　　　　　　　　logfile⽂件名

-P 　　　　　　　　　　　　 定义PLI的列表(Tab)⽂件

+v2k 　　　　　　　　　　　　　　 使⽤推荐的标准

-y 　　　　　　　　　　　　　　　 定义verilog的库

-notice 　　　　　　　　　　　　　 显⽰详尽的诊断信息

-o 　　　　　　　　　　　　　　　 指定输出的可执⾏⽂件的名字,缺省是simv

+ nospecify 　　　　　　　　　　　不对SPECIFY 模块进⾏时序检查和路径延时计算

+ notimingcheck 　　　　　　　　 不进⾏时序检查；但是还是把path延时加⼊仿真中

Summary of vcs compile options:

-ASFLAGS 　　　　"opts" pass 'opts' to the assembler

-B 　　　　　　　　generate long call instructions in native assembly code (HP only)

-CC 　　　　　　　"opts" pass 'opts' to C compiler

-CFLAGS 　　　　　"opts" pass 'opts' to C compiler

-LDFLAGS 　　　　"opts" pass 'opts' to C compiler on load line only

-I 　　　　　　　　enable interactive/postprocessing debugging capabilities

-ID 　　　　 　　　get host identification information

-M 　　　　 　　　 enable incremental compilation (see manual)

-Mupdate 　　 　　enable incremental compilation and keep the Makefile up-to-date

-Marchive[=N] 　　create intermediate libs to reduce link line length; N objs per lib

-P plitab 　　　　　compiles user-defined pli definition table 'plitab'

-PP 　　　　　　 　　enable optimizer postprocessing capabilities for vcd+

-R 　　　　　　 　　after compilation, run simulation executable

-RI 　　　　　　　　after compilation, run simulation under xvcs (Implies -I)

-RIG 　　　　　　　　run simulation under xvcs without compiling (executable has to exist)

-RPP 　　　　　　　　run xvcs in postprocessing mode (requires file created by vcdpluson)

-V[t] 　　　　 　　　verbose mode; with 't', include time information

-as 　　　　　　　　　foo use foo as the assembler

-cc 　　　　　　　　　foo use foo as the C compiler

-cpp 　　　　　　　　foo use foo as the C++ compiler

-e 　　 specify the name of your main() routine. (see manual section 7-11 for more details).

-f file 　　　　　　　　 reads 'file' for other options

-gen_c 　　　　 　　 　generate C code (for HP and Sun, default is -gen_obj)

-gen_asm 　　　　　　generate native assembly code (HP and Sun only)

-gen_obj 　　　　　　 generate native object code (HP and Sun only)

-ld 　　　　　　　　　　foo use foo as the linker. (refer vcs manual for compatibility with -cpp option)

-line 　　　　　　　　 　enable single-stepping/breakpoints for source level debugging

-lmc-swift 　　　　　　 include lmc swift interface -lmc-hm 　　　　　　　include lmc hardware modeler interface

-vera 　　 　　　　　　 add VERA 4.5+ libraries

-vera_dbind 　　　　　add VERA 4.5+ libraries for dynamic binding

-location 　　　　　　 display full pathname to vcs installation for this platform.

-vhdlobj 　　 generate a vhdl obj for simulating in a vhdl design

-mixedhdl 　　　　　　 include MixedHDL-1.0 interface

-mhdl 　　　　　　　　 include MixedHDL-2.0 interface and library

-q 　　　　　　　　　　 quiet mode

-platform. 　　　　　　 display name of vcs installation subdirectory for this platform.

-syslib 　　　　　　　　'libs' specify system libraries (placed last on the link line) eg -lm

-o 　　　　　　　　　　exec name the executable simulation model 'exec' (default is 'simv')

-u 　　　　　　　　　　 treat all non text string characters as uppercase

-v file 　　　　　　　　 search for unresolved module references in 'file'

-y libdir 　　　　　　　　　search for unresolved module references in directory 'libdir'

+acc 　　　　　　　　　　enable pli applications to use acc routines (see manual)

+ad 　　　　　　　　 　　 include anlog simulation interface and library

+adfmi="files" 　　　　　ADFMI support for vcs-ace

+cliedit 　　　　　　 　　 enable command line edit/recall (see doc/)

+cli 　　　　　　　　 　　 enable command line interactive debugging (see manual)

+cmod 　　　　　　 　　 Enabling cmodule feature

+cmodext+cmodext 　　 Changing cmodule extension to cmodext

+cmodincdir+cmoddir 　　 Cmodule Include directory

+cmoddefine+macro 　　 define cmodule source 'macro' in the form. of XX=YY

+define+macro 　　　　 　define hdl source 'macro' to have value "macro"

+plusarg_save 　　　　 　hardwire the plusargs, which follow this flag, into simv

+plusarg_ignore 　　　　 turn off +plusarg_save

+prof 　　　　　　　　 　tells vcs to profile the the design and generate file

+race 　　　　　　　　 tells vcs to generate a report of all race conditions and write this report in the file

+rad+1 　　　　　　 　　 enable level 1 radiant optimizations (See Release Notes)

+rad+2 　　　　　　 　　 enable level 2 radiant optimizations (See Release Notes)

+libext+lext 　　　　 　　 use extension 'lext' when searching library directorys

+librescan 　　　　 　　 search from beginning of library list for all undefined mods

+incdir+idir 　　　　 　　 for `include files, search directory 'idir'

+nospecify 　　　　 　　 suppress path delays and timing checks

+notimingchecks 　　 　suppress timing checks

+optconfigfile+foo 　　use 'foo' as the optimization config file (See Release Notes)

+vcsd 　　　　　　　　 enable the VCS Direct sim kernel interface

-cmhelp 　　　　　　 　enable CoverMeter help

-cm 　　　　　　　　　enable VCS to first run cmSource to instrument the Verilog source files on the command line

-cm_all 　　　　 enable VCS to link CoverMeter into the VCS executable in a way that enables all coverages

-cm_lineonly　　enable VCS to link CoverMeter into the VCS executable in a way that only enables line coverage

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+v2k

Enables language features in the IEEE 1364-2001 standard.

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success报告成功匹配

Enables reporting of successful matches, and successes on

cover statements, in addition to failures. The default is to report 04.

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only failures.

filter过滤掉空成功。

Blocks reporting of trivial implication successes. These happen

when an implication construct registers a success only because

the precondition (antecedent) portion is false (and so the

consequent portion is not checked). With this option, reporting

only shows successes in which the whole expression matches.

-assert filter+success经常两者结合起来⽤。注意⽤时在filter+success前加上-assert

maxsuccess=N

Limits the total number of reported successes to N. You must

supply N, otherwise no limit is set. VCS continues to monitor

assertions even after the limit is reached.

-assert maxsuccess=3

-l filename logfile⽂件名

Specifies a file where VCS records compilation messages. If you

also enter the -R or -RI option, VCS records messages from both

compilation and simulation in the same file.

-assert enable_diag

Enables further control of results reporting with runtime options

-sverilog

Enables the use of SystemVerilog code.

-cm assert

Compiles for SystemVerilog assertions coverage. -cm is not a

new compile-time option but the assert argument is new. This

option and argument must also be entered at runtime.

vcs *.v *.sva -sverilog

+define+enable_blk_assertions

+define+tb_sva

+define+slv_fc

+define+slv_doc

-PP -assert enable_diag -cm assert

-l

simv -l -assert filter+success -assert maxsuccess=3

VCS对verilog模型进⾏仿真包括两个步骤:

1. 编译verilog⽂件成为⼀个可执⾏的⼆进制⽂件命令为:

{1}gt; vcs source_files

2. 运⾏该可执⾏⽂件

{1}gt; ./simv

类似于NC, 也有单命令⾏的⽅式:

{1}gt; vcs source_files -R

-R 命令表⽰, 编译后⽴即执⾏.

-cm line|cond|fsm|tgl|obc|path 设定coverage的⽅式

A few more compile options are significant:

1. if RVM class libs are used in the OV code, this is required:

-ntb_opts rvm

2. VMM classes, vmm_ macros can be used in SV; and rvm_ macros

in OV package are automatically translated to vmm_ equivalents if

this is also added

-ntb_opts interop -ntb_opts rvm

-lca

这是VCS的参数，表⽰使⽤VCS的“⽤户限制使⽤”的功能，即VCS提供的⼀些功能是他们还没有经过充分测试还没有发布的；如果你想使⽤这79.

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些功能就要加上 -lca参数。

+incdir+directory

Specifies the directory or directories that VCS searches for include

files used in the `include compiler directive. More than one

directory may be specified, separated by +.

+plusarg_save

Some runtime options must be preceded by the +plusarg_save

option for VCS to compile them into the executable. You can

specify this option either on the vcs command line or in the file

specified with the -f or -F option.

You can also enter the following runtime options on the vcs command

line or in the file that you specify with the -f or -F compile-time option,

so that VCS compiles them into the simv executable, BUT you must

precede them with the +plusarg_save compile-time option:

+cfgfile +override_model_delays

+vcs+dumpoff +vcs+dumpon

+vcs+dumpvarsoff +vcs+grwavesoff

+vcs+ignorestop +vcs+learn+pli

+vcs+mipd+noalias +vcs+nostdout

+vcs+stop +vera_load

+vera_mload +vpdbufsize

+vpddrivers +vpdfile

+vpdfilesize +vpdnocompress

+vpdnostrengths +vpdports

+vpdupdate

-ntb_opts dtm

You enable testbench constructs outside programs with the

-ntb_opts dtm compile-time option and keyword argument.

The testbench constructs that you can enter outside programs with

this option are as follows:classes associative arrays dynamic arrays

SystemVerilog named events

⼯作状态: 建⽴仿真环境

VCS是Synopsys公司的仿真⼯具. VCS对verilog模型进⾏仿真包括两个步骤: 1. 编译verilog⽂件成为⼀个可执⾏的⼆进制⽂件命令为: $> vcs source_files 2. 运⾏该可执⾏⽂件 $> ./simv

类似于NC, 也有单命令⾏的⽅式: $> vcs source_files -R -R 命令表⽰, 编译后⽴即执⾏. 下⾯讲述常⽤的命令选项: -cm line|cond|fsm|tgl|obc|path 设定coverage的⽅式

+define+macro=value+ 预编译宏定义 -f filename RTL⽂件列表 +incdir+directory+ 添加include ⽂件夹 -I 进⼊交互界⾯ -l logfile⽂件名 -P 定义PLI的列表(Tab)⽂件 +v2k 使⽤推荐的标准 -y 定义verilog的库 -notice 显⽰详尽的诊断信息 -o 指定输出的可执⾏⽂件的名字,缺省是sim.v