2024年5月17日发(作者：vivoy7s上市时间)
Question:
I have a design with an incoming clock CLK that I divide by two with the
following circuit:
Figure 1: Example Circuit With Divide-by-2 Logic
Here are clocks that I have defined:
create_clock -period 10 CLK
create_generated_clock
-name CLKdiv2
-divide_by 2
-source [get_ports CLK]
[get_pins Udiv/Q]
These clocks are reported by the report_clocks command as follows:
pt_shell> report_clocks
****************************************
Report : clock
...
****************************************
Attributes:
p - Propagated clock
G - Generated clock
I - Inactive clock
Clock Period Waveform Attrs Sources
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