2024年3月23日发(作者：oppok10为什么停产了)

SECTION 8 SYNCHRONOUS SERIAL PERIPHERAL INTERFACE

The serial peripheral interface (SPI) is one of two independent serial communications

subsystems included on the MC68HC11A8. As the name implies, the SPI is primarily

used to allow the microcontroller unit (MCU) to communicate with peripheral devices.

The SPI is also capable of interprocessor communications in a multiple-master sys-

tem. Peripheral devices are as simple as an ordinary transistor-transistor logic (TTL)

shift register or as complex as a complete subsystem, such as a liquid crystal diode

(LCD) display driver or an analog-to-digital (A/D) converter subsystem. The SPI sys-

tem is flexible enough to interface directly with numerous standard product peripherals

from several manufacturers. The system can be configured as a master or a slave de-

vice. Data rates as high as 1 Mbit per second are accommodated when the system is

configured as a master; rates as high as 2 Mbits per second are accommodated when

the system is operated as a slave.

Clock control logic allows a selection of clock polarity and a choice of two fundamen-

tally different clocking protocols to accommodate most available synchronous serial

peripheral devices. When the SPI is configured as a master, software selects one of

four different bit rates for the serial clock.

Error-detection logic is included to support interprocessor communications. A write-

collision detector indicates when an attempt is made to write data to the serial shift reg-

ister while a transfer is in progress. A multiple-master mode-fault detector automatical-

ly disables SPI output drivers if more than one MCU simultaneously attempts to

become bus master.

The I/O pin control logic on the MC68HC11A8 is more flexible than that of other Mo-

torola MCUs. This added I/O pin control allows the MC68HC11A8 to implement sys-

tems with a single, bidirectional data line or other unusual synchronous serial

configurations.

8.1 SPI Transfer Formats

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and re-

ceived (shifted in serially). A serial clock line synchronizes shifting and sampling of the

information on the two serial data lines. A slave select line allows individual selection

of a slave SPI device; slave devices that are not selected do not interfere with SPI bus

activities. On a master SPI device, the slave select line can optionally be used to indi-

cate a multiple-master bus contention.

8.1.1 SPI Clock Phase and Polarity Controls

Software can select any of four combinations of serial clock (SCK) phase and polarity

using two bits in the SPI control register (SPCR). The clock polarity is specified by the

CPOL control bit, which selects an active high or active low clock and has no signifi-

cant effect on the transfer format. The clock phase (CPHA) control bit selects one of

M68HC11SYNCHRONOUS SERIAL PERIPHERAL INTERFACEMOTOROLA

REFERENCE MANUAL8-1

8

two fundamentally different transfer formats. The clock phase and polarity should be

identical for the master SPI device and the communicating slave device. In some cas-

es, the phase and polarity are changed between transfers to allow a master device to

communicate with peripheral slaves having different requirements. The flexibility of the

SPI system on the MC68HC11A8 allows direct interface to almost any existing syn-

chronous serial peripheral.

8.1.2 CPHA Equals Zero Transfer Format

Figure 8-1 is a timing diagram of an SPI transfer where CPHA is zero. Two waveforms

are shown for SCK: one for CPOL equals zero and another for CPOL equals one. The

diagram may be interpreted as a master or slave timing diagram since the SCK, mas-

ter in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected be-

tween the master and the slave. The MISO signal is the output from the slave, and the

MOSI signal is the output from the master. The SS line is the slave select input to the

slave; the SS pin of the master is not shown but is assumed to be inactive. The SS pin

of the master must be high or must be reconfigured as a general-purpose output not

affecting the SPI. This timing diagram functionally depicts how a transfer takes place;

it should not be used as a replacement for data-sheet parametric information.

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

*

Not defined but normally MSB of character just received.

MSB

MSB

6

6

5

5

4

4

3

3

2

2

1

1

LSB

LSB

*

12345678

8

Figure 8-1 CPHA Equals Zero SPI Transfer Format

8.1.3 CPHA Equals One Transfer Format

Figure 8-2

is a timing diagram of an SPI transfer where CPHA is one. Two waveforms

are shown for SCK: one for CPOL equals zero and another for CPOL equals one. The

diagram may be interpreted as a master or slave timing diagram since the SCK, MISO,

and MOSI pins are directly connected between the master and the slave. The MISO

signal is the output from the slave, and the MOSI signal is the output from the master.

The SS line is the slave select input to the slave; the SS pin of the master is not shown

but is assumed to be inactive. The SS pin of the master must be high or must be re-

configured as a general-purpose output not affecting the SPI. This timing diagram

functionally illustrates how a transfer takes place; it should not be used as a replace-

ment for data-sheet parametric information.

MOTOROLA

8-2

SYNCHRONOUS SERIAL PERIPHERAL INTERFACEM68HC11

REFERENCE MANUAL