2024年2月20日发(作者：联想家悦机箱拆机图解)

LM98725LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output,

Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock

GenerationLiterature Number: SNAS474D/

LM987253 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor TimingGenerator and Spread Spectrum Clock GenerationGeneral DescriptionThe LM98725 is a fully integrated, high performance 16-Bit,81 MSPS signal processing solution for digital color copiers,scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative archi-tecture utilizing Correlated Double Sampling (CDS), typicallyemployed with CCD arrays, or Sample and Hold (S/H) inputs(for higher speed CCD or CMOS image sensors). The signalpaths utilize 8 bit Programmable Gain Amplifiers (PGA), a+/-9-Bit offset correction DAC and independently controlledDigital Black Level correction loops for each input. The PGAand offset DAC are programmed independently allowingunique values of gain and offset for each of the three analoginputs. The signals are then routed to a 81MHz high perfor-mance analog-to-digital converter (ADC). The fully differentialprocessing channel shows exceptional noise immunity, hav-ing a very low noise floor of -74dB. The 16-bit ADC hasexcellent dynamic performance making the LM98725 trans-parent in the image reproduction chain.A very flexible integrated Spread Spectrum Clock Generation(SSCG) modulator is included to assist with EM complianceand reduce system Sensor Timing Generator and Spread Spectrum Clock GenerationFeatures■■■■■■■■LVDS/CMOS OutputsLVDS/CMOS/Crystal Clock Source with PLL MultiplicationIntegrated Flexible Spread Spectrum Clock GenerationCDS or S/H Processing for CCD or CIS sensorsIndependent Gain/Offset Correction for Each ChannelAutomatic per-Channel Gain and Offset CalibrationProgrammable Input Clamp VoltageFlexible CCD/CIS Sensor Timing GeneratorKey Specifications■■■■■■■■■■■■■■■■1.2 or 2.4 Volt Modes(both with + or - polarity option)ADC Resolution16-BitADC Sampling Rate81 MSPSINL+17/- 28 LSB (typ)Channel Sampling Rate30/30/27 MSPSPGA Gain Steps256 StepsPGA Gain Range0.62 to 8.3xAnalog DAC Resolution+/-9 BitsAnalog DAC Range+/-307mV or +/-614mVDigital DAC Resolution+/-6 BitsDigital DAC Range-2048 LSB to + 2016 LSBSNR-74dB (@0dB PGA Gain)Power Dissipation755mW (LVDS)Operating Temp0 to 70°CSupply Voltage3.3V Nominal (3.0V to 3.6V range)Maximum Input LevelApplications■■■■Multi-Function PeripheralsHigh-speed Currency/Check ScannersFlatbed or Handheld Color ScannersHigh-speed Document ScannersSystem Block Diagram30085370© 2009 National Semiconductor p:///

LM30085301FIGURE 1. Chip Block 2/

72530085302FIGURE 2. LM98725 Pin Out p:///

4/30085373

725Pin1234NamePHIC2PHIC1SH1CEI/OOOOITypDDDDResPUPDPU

DescriptionConfigurable high speed sensor timing urable high speed sensor timing urable low speed sensor timing Serial Interface Address Setting InputCE LevelVDFloatDGNDAddress682936CALRESETSH_RSDISDOSCLKSENVAAGNDVAVREFBVREFTVAAGNDVCLPVAIBIASAGNDOSRAGNDOSGAGNDOSBCPOFILT2DGNDCPOFILT1DVBINCLK+INCLK-DOUT7/TXCLK+DOUT6/TXCLK-DOUT5/TXOUT2+IIIIOII

OO

IO

O

I

I

I

OIIOOODDDDDDDPPPAAPPAPAPAPAPAAPADDDDDDPDPUPDPD

PDPU

Initiate calibration sequence. Leave unconnected or tie to DGND if -low master reset. NC when function not being al request for an SH Interface Data Interface Data Interface shift register -low chip enable for the Serial power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to ground power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to of ADC reference. Bypass with a 0.1μF capacitor to of ADC reference. Bypass with a 0.1μF capacitor to power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to ground Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to external reference voltage may be applied to this power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to setting pin. Connect a 9.0 kOhm 1% resistor to ground input signal. Typically sensor Red output AC-coupled thru a ground input signal. Typically sensor Green output AC-coupled thru a ground input signal. Typically sensor Blue output AC-coupled thru a Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor l ground Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor l Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock isselected when pin 29 is held at DGND, otherwise clock is configured for LVDS Input. Inverting input for LVDS clocks, connect to DGND for CMOS 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS p:///

LM3738394647484956DOUT4/TXOUT2-DOUT3/TXOUT1+DOUT2/TXOUT1-DOUT1/TXOUT0+DOUT0/TXOUT0-DGNDVDVCCLKOUT/SH2SH3RSCPPHIA1PHIA2DGNDVCPHIB1PHIB2SH4SH5OOOOOO

OOOOOO

OOOODDDDDDPPDDDDDDPPDDDD

PD

Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS MoBit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS MBit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS MoBit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS MBit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS MoConfigurable sensor control supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A s4.7μF capacitor should be used between the supply and the VD, VR and VC supply for the sensor control outputs. Bypass this supply pin with 0.1μF capaOutput clock for registering output data when using CMOS outputs, or a configuralow speed sensor timing urable low speed sensor timing urable high speed sensor timing urable high speed sensor timing urable high speed sensor timing urable high speed sensor timing l ground supply for the sensor control this supply pin with 0.1μF urable high speed sensor timing urable high speed sensor timing urable low speed sensor timing urable low speed sensor timing output.(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal 6/

2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and Voltage (VA,VR,VD,VC)Voltage on Any Input Pin(Not to exceed 4.2V)Voltage on Any Output Pin(execpt DVB and not to exceed 4.2V)DVB Output Pin VoltageInput Current at any pin other thanSupply Pins (Note 3)Package Input Current (except SupplyPins) (Note 3)Maximum Junction Temperature (TA)4.2V−0.3V to(VA + 0.3V)−0.3V to(VA + 0.3V)2.0V±25 mA±50 mA150°CPackage Dissipation at TA = 25°C>1.89W(Note 4)ESD Rating (Note 5) Human Body Model2500V Machine Model250VStorage Temperature−65°C to +150°CSoldering process must comply with NationalSemiconductor’s Reflow Temperature Profilespecifications. Refer to /packaging.(Note 6)725Operating Ratings

Operating Temperature RangeAll Supply Voltage(Note 1, Note 2)0°C

≤ TA

≤ +70°C+3.0V to +3.6VElectrical CharacteristicsThe following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 27MHz unless otherwise ce limits apply for TA = TMIN to TMAX; all other limits TA = 25°ParameterConditionsMin(Note 9)2.0

Typ(Note 8)

0.6

1006530

-65-100-303.0

18-2520-25

2.30.1212-1420-25 nA

VVmA nA

0.21

Max(Note 9)

0.8

UnitsCMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)VIHVILVIHYSTIIHLogical “1” Input VoltageLogical “0” Input VoltageLogic Input HysteresisLogical “1” Input Current

VIH

= VDRESET,SENSH_R, SCLK, SDI, CALCEIILLogical “0” Input CurrentVIL = DGNDRESETSENSH_R, SCLK, SDI, CALCECMOS Digital Output DC Specifications (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC)VOHVOLIOSIOZLogical “1” Output VoltageLogical “0” Output VoltageOutput Short Circuit CurrentCMOS Output TRI-STATE CurrentIOUT = -0.5mAIOUT = 1.6mAVOUT = DGNDVOUT= VDVOUT = DGNDVOUT = VDCMOS Digital Output DC Specifications (CMOS Data Outputs)VOHVOLIOSIOZLogical “1” Output VoltageLogical “0” Output VoltageOutput Short Circuit CurrentCMOS Output TRI-STATE CurrentIOUT = -0.5mAIOUT = 1.6mAVOUT = DGNDVOUT= VDVOUT = DGNDVOUT = VDLVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)VVmAVV

nAμAnA

μAnAμp:///

LM(Note 9)VIHLDifferential LVDS ClockHigh Threshold VoltageVILLVIHCVILCIIHLIILCDifferential LVDS ClockLow Threshold VoltageCMOS ClockHigh Threshold VoltageCMOS ClockLow Threshold VoltageCMOS ClockInput High CurrentCMOS ClockInput Low CurrentDifferential Output VoltageLVDS Output Offset VoltageOutput Short Circuit CurrentVA Analog Supply CurrentVOUT = 0V, RL = 100ΩLVDS Output Data FormatLVDS Output Data Format(Powerdown)CMOS Output Data Format(40 MHz)IDVD Digital Output Driver SupplyCurrentLVDS Output Data FormatLVDS Output Data Format(Powerdown)CMOS Output Data Format(ATE Loading of CMOS Outputs> 50 pF) (40 MHz)ICVC CCD Timing Generator OutputDriver Supply CurrentTypical sensor outputs:SH1-SH5, PHIA, PHIB, PHIC,RS, CP(ATE Loading of CMOSOutputs > 50pF)LVDS Output Data FormatLVDS Output Data Format(Powerdown)CMOS Output Data Format(ATE Loading of CMOS Outputs> 50pF) (40 MHz)Input Sampling Circuit SpecificationsVINInput Voltage LevelCDS Gain=1x, PGA Gain=1xCDS Gain=2x, PGA Gain= 1x

RL = 100ΩVCM (LVDS Input Common ModeVoltage)= 1.25V

INCLK- = DGND2.0

-135

(Note 8)

(Note 9)200mV-200

230-120

0.8260

mVVVμAμALVDS Output DC SpecificationsVODVOSIOSIARL = 100Ω2801.08

3901.208.51523.6136768.5464901.33

18mVVmAPower Supply SpecificationsmAmAmAmAmAmA 14mAPWRAverage Power Dissipation

7554mWmWmW2.31.22 8/

(Note 9)IIN_SHSample and Hold ModeInput Leakage Current

CSHSample/Hold ModeEquivalent Input Capacitance

CDS ModeInput Leakage CurrentCLPIN Switch Resistance(OSX to VCLP Node)VCLP Voltage 000VCLP Voltage 001VCLP Voltage 010VVCLPVCLP Voltage 011VCLP Voltage 100VCLP Voltage 101VCLP Voltage 110VCLP Voltage 111ISCVCLP DAC Short Circuit OutputCurrentResolutionMonotonicityOffset Adjustment RangeReferred to AFE Input

Offset Adjustment RangeReferred to AFE Output

DNLINLDAC LSB Step SizeDifferential Non-LinearityIntegral Non-LinearitySource Followers OffCDS Gain = 1xOSX = VA (OSX = AGND)Source Followers OffCDS Gain = 2xOSX = VA (OSX = AGND)Source Followers OnCDS Gain = 2xOSX = VA (OSX = AGND)CDS Gain = 1xCDS Gain = 2xSource Followers OffOSX = VA (OSX = AGND)

(-200)

(-290)

(-250)

(-250)

(Note 8)32(-165)

55(-240)

20(-50)

2.5410(-50)16(Note 9)50

70

250

250

55μA725μAnApFpFnAΩIIN_CDSRCLPINVCLP Reference Circuit SpecificationsVCLP Voltage Setting = 000VCLP Voltage Setting = 001VCLP Voltage Setting = 010VCLP Voltage Setting = 011VCLP Voltage Setting = 100VCLP Voltage Setting = 101VCLP Voltage Setting = 110VCLP Voltage Setting = 1110001 xxxxb VCLP er =

CDS Gain = 1xMinimum DAC Code = 0x000Maximum DAC Code = 0x3FFCDS Gain = 2xMinimum DAC Code = 0x000Maximum DAC Code = 0x3FFMinimum DAC Code = 0x000Maximum DAC Code = 0x3FFCDS Gain = 1xReferred to AFE Output

0.85VA0.9VA0.95VA0.6VA0.55VA0.4VA0.35VA0.15VA30

VVVVVVVVmABlack Level Offset DAC Specifications

10

-614614

-307307

1.2(32)+0.74/-0.37+0.72/-0.5688.318.4

mV

mV-16130+17500

+2.4+2.5BitsGuaranteed by characterization

-17500+16130

-0.84-2.5LSBmV(LSB)LSBLSBPGA Specifications

Gain ResolutionMonotonicityMaximum Gain

CDS Gain = 1xCDS Gain = 1x7.717.7

8.818.9BitsV/VdBGuaranteed by p:///

分销商库存信息:NATIONAL-SEMICONDUCTORLM98725CCMT/NOPBLM98725CCMTX/NOPB