Si52204最高性能和最低功耗解决方案

Si52204最高性能和最低功耗解决方案


2024年3月30日发(作者:)

Silabs Si52204最高性能和最低功耗PCI总线时钟解决方案

Silabs公司的Si52212/08/04/02是业界最高性能和最低功耗PCIe时钟发生器,具有单独的硬件控制引脚,启用

和禁用每个输出,扩展频谱启用和禁用用于降低EMI,可选择100, 133或200 MHz不同输出频率.这些频率可通

过I2C来控制.Si52212/08/04/02的小占位和低功耗,使这些PCIe时钟发生器非常适合工业和消费类电子应用.

器件输出低功率推挽HCSL和PCI-Express Gen 1, Gen 2,Gen 3, Gen 4, Gen 5以及SRIS兼容.低抖动为0.13ps,三

角扩展频谱可降低EMI 0.25%或0.5%,内部100 Ω 或85 Ω线路匹配,可调输出转换速率.25MHz晶振输入或时

钟输入,I2C支持回读功能,工作电压1.5V-1.8V,工作温度–40到85℃,小型QFN封装,主要用在服务器,存储设备,

数据中心,PCIe附加卡,网络接口卡(NIC),图像适配卡,多功能打印机,数字单反(DSLR)照相机,数字相机,数字摄像

机和坞站.本文介绍了Si52212/08/04/02主要特性和特性列表,框图以及评估板Si52204-EVB主要特性,框图,

电路图,材料清单和PCB设计图

The Si52212, Si52208, and Si52204 can source twelve, eight, and four 100 MHz PCIe differential clock outputs,

respectively, plus one 25 MHz LVCMOS reference clock output. The Si52202 can source two 100 MHz PCIe clock

outputs only. All differential clock outputs are compliant to PCIe Gen1/2/3/4/5 common clock and separate

reference clock architectures specifications.

The Si52212/08/04/02 feature individual hardware control pins for enabling and disabling each output, spread

spectrum enable/disable for EMI reduction, and frequency select to select 100, 133, or 200 MHz differential

output frequencies. These features canalso be controlled via I2C.

The small footprint and low power consumption make this family of PCIe clock generators ideal for industrial and

consumer applications.

For more information about PCI-Express, Silicon Labs’complete PCIe portfolio, applicationnotes, and design tools,

including the Silicon Labs PCIe Clock Jitter Tool for PCIExpresscompliance, please visit the Silicon Labs PCI Express

Learning Center.

Si52212/08/04/02主要特性:

• 12/8/4/2-output low-power, push-pull HCSLcompatible PCI-Express Gen 1, Gen 2,Gen 3, Gen 4, Gen 5, and

SRIS-compliantoutputs

• Low jitter: 0.13 psrms max, Gen 5

• Individual hardware control pins and I2Ccontrols for Output Enable, SpreadSpectrum Enable and Frequency

Select

• Triangular spread spectrum for EMIreduction, down spread 0.25% or 0.5%

• Internal 100 Ω or 85 Ω line matching

• Adjustable output slew rate

• Power down (PWRDNb) function supportsWake-on LAN (except Si52202)

• One non-spread, LVMCOS reference clockoutput (except Si52202)

• Frequency Select to select 133 MHz or200 MHz (except Si52202)

• 25 MHz crystal input or clock input

• I2C support with readback capabilities

• Extended temperature: –40 to 85 ℃

• 1.5–1.8 V power supply, with separateVDD and VDD_IO

• Small QFN packages

• Pb-free, RoHS-6 compliant

Si52212/08/04/02应用:

• Servers

• Storage

• Data Centers

• PCIe Add-on Cards

• Network Interface Cards (NIC)

• Graphics Adapter Cards

• Multi-function Printers

• Digital Single-Lens Reflex (DSLR) Cameras

• Digital Still Cameras

• Digital Video Cameras

• Docking Stations

Si52212/08/04/02特性列表:

• 12/8/4/2-output 100 MHz PCIe Gen 1/2/3/4/5 and SRIS compliant clock generator, with push-pull HCSL output

drivers

• High port count with push-pull HCSL outputs to support highly integrated solution, eliminating external resistors

for the HCSL outputdrivers

• Low jitter of 0.13 psrms max to meet PCIe Gen5 specifications with design margin

• Low power consumption.

• Lowest power consumption in the industry for a 2-output PCIe clock generator

• Individual hardware control pins and I2C controls for Output Enable, Spread Spectrum Enable and Frequency

Select

• Output Enable function easily disables unused outputs for power saving

• Spread Enable function to turn on/off spread spectrum and to select spread levels, either down spread 0.25% or

0.5%

• Frequency Select function to select output frequency of 100 MHz, 133 MHz, or 200 MHz (except Si52202 where

the output frequencyis limited to 100 MHz. Please contact Silicon Labs for 133 MHz or 200 MHz in Si52202)

• All above functions are controlled by individual hardware pins or I2C

• Internal 100 Ω or 85 Ω impedance matching

• Eliminates external line matching resistor to reduce board space

• Adjustable slew rate to improve signal quality for different applications and board designs

• Power down (PWRDNb) function supports Wake-on LAN (except Si52202)

• One non-spread, 25 MHz LVMCOS reference clock output (except Si52202)

• A buffered 25 MHz LVCMOS clock output to drive ASICS or SoCs on board

• 25 MHz reference input

• Supports a standard crystal or clock input for flexibility


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